An NMOS cascode amplifier using an active current-source load in place of a resistive one. Swapping the load raises output resistance by orders of magnitude, and gain rises with it.

QuantityValue
Device sizing\(W = 20\ \mu\mathrm{m}\), \(L = 1\ \mu\mathrm{m}\)
Bias current\(I_D = 1\ \mathrm{mA}\)
Transconductance (hand-calculated)\(g_m = 2.83\ \mathrm{mS}\)
Output resistance per device\(r_o \approx 50\ \mathrm{k\Omega}\)
Amplifier output resistance\(\approx 7.2\ \mathrm{M\Omega}\)
Voltage gain\(86\ \mathrm{dB}\)

Transconductance and output resistance were hand-calculated from SPICE Level-1 model parameters (\(K_P = 200\ \mu\mathrm{A/V}^2\), \(V_T = 1.0\ \mathrm{V}\), \(V_{ov} = 0.707\ \mathrm{V}\)) before simulating, then gain and bandwidth were verified against LTspice AC analysis from 10 Hz to 100 MHz.

LTspice schematic of the cascode amplifier: stacked NMOS devices M1 and M2, a 1 mA current-source load to a 5 V rail, 2.5 V cascode bias, and the SPICE model card
LTspice schematic. M1 and M2 stacked as the cascode, a 1 mA current source as the active load, and the Level-1 model card driving an AC sweep from 10 Hz to 100 MHz.

Hand analysis

Handwritten derivation for the cascode amplifier: device sizing, K from KP times W over L, overdrive voltage, transconductance, output resistance per device, total output resistance, and the resulting voltage gain in decibels
The derivation worked by hand before simulating: \(K = K_P (W/L)\), then \(V_{ov}\), \(g_m = K V_{ov} = 2.83\ \mathrm{mS}\), \(r_o = 1/(\lambda I_D) = 50\ \mathrm{k\Omega}\), \(R_{out} \approx (1 + g_{m2} r_{o2})r_{o1} + r_{o2} = 7.17\ \mathrm{M\Omega}\), giving \(|A_v| = 20\log_{10}(20{,}280) = 86.14\ \mathrm{dB}\).
LTspiceCMOS Cascode topologyActive load Hand analysis → simulation